1. Field of the Invention. This invention relates to packaging techniques for integrated circuits and more particularly to techniques for connecting the leads of a lead frame to a printed circuit substrate on which is mounted an integrated-circuit die.
2. Prior Art, A conventional high-performance plastic quad flat pack (HP PQFP) package for an integrated-circuit uses a substrate, such as a multi-layer printed circuit board (PCB), having multiple connection layers formed thereon. These multiple connection layers are used to provide power, ground, and signal connections to an integrated-circuit die attached to the substrate. The impedance and capacitance of the various connections are controlled with this type of printed-circuit structure so that the electrical performance of an integrated circuit packaged in this manner can be controlled.
In this type of package, the multiple connection layers are fabricated as laminated layers of a multi-layer printed-circuit board (PCB) assembly. The multi-layer printed-circuit board (PCB) is located in the center area of the lead frame, with the leads of the lead frame extending outwardly from the PCB. During a conventional fabrication process, the lead frame is typically formed as an integral part of the multi-layer printed-circuit board assembly so that the area of the lead frame is much greater than the area of the printed-circuit board PCB.
A number of printed-circuit board assemblies, each of which includes a printed-circuit board and an associated, integrally-formed lead frame, are formed in a batch in a large printed circuit board. This is expensive because the area of the large printed circuit board lying beneath the leads of the lead frame is not used. Each of these printed-circuit board assemblies takes up a large area of the large printed circuit board, with much of the area of the large printed circuit board not being used for a multi-layer structure. The printed-circuit board assemblies are typically fabricated in strips of four or five each on the large printed circuit board.
The three major cost components of a conventional high-performance plastic quad flat pack package assembly produced in the above manner are: (1) the number of units created per large PCB; (2) the defect density per strip; and (3) the processing cost for the integrated lead frame. Less than 30% of the usable area of the large PCB is used to manufacture the multi-layer structure. The rest of the area is used only for the lead frame. Over 30% of 4-up lead-frame strips contains at least one defective multi-layer and 50% of 5-up lead-frame strips contains at least one defective multi-layer structure. If a 4-up strip containing a single defective multi-layer structure is scrapped, the yield for that strip is 60-70%. If a 5-up strip containing a single defective multi-layer structure is scrapped, the yield for that strip is 40-50%.
Etching technology is used to manufacture a conventional, integral metal-layer lead frame for a plastic quad flat pack. Etching operations for forming an integral lead frame are much more expensive than conventional stamping operations for forming a separate lead frame. Conventional plastic quad flat pack package designs include a multi-layer PCB structure with a die cavity. The die, cavity limits both the maximum and the minimum die sizes which can be used with a given multi-layer PCB structure.
U.S. Pat. No. 4,846,700, granted on Jul. 11, 1990, to Richard K. Dennis, discloses a lead frame having rows of leads which are connected to the edges of a semiconductor device. Each of the ends, or heads, of each lead is split in two parts. One part of the split end is called an uppermost leg and the other part is called a lowermost leg. To assemble the leads to the edges of a semiconductor device, the rows of leads are bent away from the horizontal plane of the lead frame to position the spaces between the uppermost legs and the lowermost legs to receive the edges of the semiconductor device. The rows of split leads are then released and the split leads return to the horizontal plane so that the uppermost legs and the lowermost legs of each split lead hold the edges of the semiconductor device. Each split lead thus is attached to an edge of the semiconductor device with both an uppermost leg and a lowermost leg. Each connection thus takes two legs, each of which leg occupies the same amount of horizontal area in the lead frame so that each connection to the semiconductor device takes an area equal to the area of two legs.
U.S. Pat. No. 4,870,224, granted on Sep. 26, 1989, to William D. Smith et al., discloses an integrated-circuit device which is fixed to a ceramic substrate. Conductors are formed on the ceramic substrate and extend from the integrated-circuit device to the edges of the ceramic substrate. The ends of each of the leads of a lead frame are forked to include an upper finger and two lower forked fingers. The substrate is fixed between the three fingers and the fingers are soldered to respective sides of the substrate. The three fingers of each split lead are horizontally spaced apart and occupy the same amount of horizontal space so that each connection to the ceramic substrate takes an area equal to the area of three fingers.
Connection designs which incorporate leads with legs or fingers which contact both sides of a semiconductor device or a substrate, as disclosed in the above referenced patents, use two or three times the amount of area than does a design using a single leg or finger. With the increased need for packages having greater numbers of fine-pitched leads, the use of lead frames with leg or finger designs which use large amounts of area is limited. Consequently, the need exists for an integrated-circuit connection design which has increased lead density while; using minimal area.